The invention relates to segmented digital-to-analog converters (DACs), and more particularly to segmented string DACs, and still more particularly to LSB interpolation circuits which avoid large non-linearities that are associated with prior interpolation circuits that modulate the offset voltage of a differential buffer amplifier in response to LSB subword signals applied to the DAC.
Those skilled in the art know that various DAC architectures are available, including clocked DACs and static DACs. It is also known that a static DAC architecture should be used if low, long term drift performance is required. Some static DAC architectures, such as those including R2R ladder networks and those including switched current sources, are not inherently monotonic and must either be "trimmed" or digitally calibrated, at substantial additional cost to ensure the monotonicity which is essential for some applications.
String DACs are a type of static DAC that includes a plurality of resistors connected in series between a high reference voltage and a low reference voltage, wherein the various connecting nodes between the resistors constitute tap points that are selectively switched to an output node in response to the digital input, and the voltage of the tap point selectively switched to the output node is an inherently monotonic analog representation of the digital input. For an N-bit DAC, 2.sup.N -1 tap point voltage levels are required, so 2.sup.N resistors are required for a string DAC. This number of resistors is too large to be practical for more than approximately eight bits, unless the DAC is segmented into a string DAC section and an interpolation DAC section, in which case the interpolation section also must be inherently monotonic to ensure that the entire DAC is monotonic.
The closest prior art is believed to be U.S. Pat. No. 5,396,245, issued Mar. 7, 1995 to William C. Rempfer and assigned to Linear Technology Corporation; this patent discloses a string DAC with a monotonic interpolation circuit. Since both the string DAC section and the interpolation section are inherently monotonic, the entire DAC also is inherently monotonic. FIG. 1 hereof is a copy of FIG. 5 of the '245 patent.
Referring to FIG. 1, the prior art segmented DAC 500 includes a string 401 of resistive elements all of equal resistance. The lower terminal of each resistive element is connected by a corresponding lower switch to a first conductor, and the upper terminal of each resistive element is connected by a corresponding upper switch to a second conductor. A pair of switches constituting a lower switch and an upper switch thus is associated with each resistive element. An "MSB subword" of the digital input word applied to DAC 500 is decoded to close one of the pairs of switches so that the difference between a voltage V.sub.2 produced on the second conductor and a voltage V.sub.1 produced on the first conductor is the voltage drop across the associated resistive element of resistive string 401. The string of resistors 401 and the corresponding set of pairs of switches 402 constitute a "string DAC", and the voltage V.sub.1 is a "coarse" analog representation of the MSB subword. The coarse analog representation V.sub.1 is necessarily monotonic because an increased value of the MSB digital input subword always results in an increased value of V.sub.1. 2.sup.M resistive elements are used in resistive string 401 if the MSB subword has M bits.
The segmented DAC 500 of prior art FIG. 1 also includes an interpolation DAC which produces a "fine" interpolation of the voltage drop V.sub.2 -V.sub.1 across the resistive element selected by the M-bit MSB subword, wherein the interpolation occurs in response to an N-bit LSB subword. The interpolation DAC includes a single differential transconductance stage 408 in which monotonicity is assured by modulation of the offset voltage of the differential transconductance stage 408. This is accomplished by providing 2.sup.N P-channel "subtransistors" 409a, 409b, 409c, and 409d in block 409 and 2.sup.N P-channel subtransistors 410a,b,c,d in block 410, with the source electrodes of subtransistors 409a,b,c,d and 410a,b,c,d connected to a single tail current source 411. The gate of subtransistor 409a is permanently connected to V.sub.1. The gates of subtransistors 409b,c,d are selectively connected to either V.sub.1 or V.sub.2 by switches 405, 406, and 407, respectively in response to the decoding of the N-bit LSB subword. For an N-bit LSB subword, there would be 2.sup.N -1 such switches and 2.sup.N subtransistors in block 409, and the N-bit LSB subword is decoded so as to select various combinations of the subtransistors 409b,c,d so that each increment in the value of the N-bit LSB subword switches the gate of an additional one of subtransistors 409b,c,d from V.sub.1 to V.sub.2.
The gates of subtransistors 410a,b,c,d all are connected to the output of an inverting amplifier 108 having its input connected to the first output of differential transconductance stage 408. The input of amplifier 108 is connected to the drain electrodes of subtransistors 409a,b,c,d and the drain electrode of an N-channel transistor 105 having its source connected to V- and its gate connected to the gate and drain of an N-channel transistor 106 having its source connected to V-. The drain of transistor 106 is connected to the drains of subtransistors 410a,b,c,d. N-channel transistors 105 and 106 constitute a current mirror load circuit for differential transconductance stage 408. The subtransistors 409a-d and the subtransistors 410a-d have substantially equal geometries.
Incrementing the N-bit LSB subword by one causes the 2.sup.N -1 switches in block 404 to switch one more of the subtransistors 409b,c,d from V.sub.1 to V.sub.2, which modulates the input offset voltage of differential transconductance stage 408. This ensures that DAC 500 of prior art FIG. 1 provides monotonic digital-to-analog conversion.
Unfortunately, the interpolation DAC of prior art FIG. 1 is very non-linear. Curve A of FIG. 4 shows the large, non-linear error as a function of the LSB subword value.
Accordingly, there is a need for a segmented DAC including a resistive MSB string DAC and an LSB interpolation DAC that ensures a monotonic output as is accomplished by the circuit of prior art FIG. 1, but without the non-linearity caused by the interpolation DAC.